1. Field of the Invention
The present invention relates to a device which shares a memory bus. More particularly, the present invention relates to a device which uses a no operation (NOP) command to share a memory bus, which can reduce a size of a chipset and manufacturing costs of the chipset.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional computer architecture.
Referring to FIG. 1, a computer 100 includes a microprocessor 110, a chipset 120, a main memory 130 and a peripheral device 140. The microprocessor 110 is a central processing unit (CPU) or a CPU and a circuit related to it. The chipset 120 is an integration of circuits in the computer 100. The microprocessor 110 accesses data stored in the main memory 130 and communicates the data to the peripheral device 140 through the chipset 120. The main memory 130 stores programs and data used by the microprocessor 110. The main memory 130 includes synchronous dynamic random access memory (SDRAM). Commands used for SDRAM include precharge, read, write activate and no operation (NOP). The peripheral device 140 includes a hard disk, a floppy disk or a RS232 interface.
Although the circuit in the chipset can be complex in design to that it has many functions, the pin count of the chipset is limited by the size of the chipset.
In general, the chipset is a ball-grid array device having 492 pins. Two sets of control circuits are usually integrated into the device, in which one is a memory control circuit and the other is a graphic control circuit, to decrease manufacturing costs. However, the pin count of the chipset has risen to 556 as other peripheral control circuits have been integrated into the chipset. The manufacturing costs are increased and the size of the chipset is also increased.